1. Field of the Invention
The present invention relates to methods for manufacturing electrically erasable and programmable non-volatile memory cells or EEPROM cells and to memory cells obtained with such methods.
2. Discussion of the Related Art
An EEPROM cell generally comprises a selection element and a storage element. As an example, the selection element corresponds to a MOS transistor and the storage element corresponds to a dual-gate MOS transistor comprising a floating gate covered with a control gate. The floating gate insulator comprises a thinned-down portion at the level of the dual-gate transistor drain which forms a tunnel window.
The operation of such a memory cell is the following. An erasing operation in the memory cell is performed by turning on the selection transistor, by setting the drain and the source of the dual-gate transistor to 0 volt, and by setting the control gate of the dual-gate transistor to a given voltage. This causes the passing of charges from the drain to the floating gate of the dual-gate transistor through the tunnel window and the storage of charges in the floating gate. A write operation in the memory is performed by turning on the selection transistor, by applying a write voltage between the drain and the source of the dual-gate transistor and by maintaining the control gate of the dual-gate transistor at 0 volt. This causes the evacuation of the charges stored in the floating gate through the tunnel window. A read operation is performed by turning on the selection transistor, by applying a read voltage, smaller than the write voltage, between the drain and the source of the dual-gate transistor, and by setting the control gate of the dual-gate transistor to a given voltage. The magnitude of the current conducted by the dual-gate transistor is representative of the presence or of the absence of charges in the floating gate.
Conventional methods for manufacturing such a memory cell generally comprise several photolithographic etch steps requiring use of masks. As an example, a first mask is used to delimit the source and drain regions of the dual-gate transistor and a second mask is used to delimit the tunnel window.
A critical point on manufacturing of the dual-gate transistor is the positioning of the drain region with respect to the tunnel window, that is, the positioning of the first mask relative to the second mask. Indeed, to ensure a proper operation of the dual-gate transistor, it is necessary for the drain region to extend under the entire tunnel window and to extend slightly beyond the tunnel window. It is desirable for this extension or projection of the drain region out of the tunnel window to be as small as possible to enable decreasing the memory cell dimensions. However, given the accuracy of currently-used mask positioning methods, it is generally necessary to provide a minimum projection greater than 0.1 μm. It is further desirable for the projection to be substantially the same from one memory cell to the other to ensure a homogeneity of the operating properties of memory cells. Memory cells being generally formed in pairs of adjacent cells symmetrical with respect to the common edge between cells, a misalignment between the first and second masks translates as projections which are different between the two asymmetrical cells. The operating properties of the memory cells of a same memory may then not be identical (odd/even effect).